1. Field of the Invention
The present invention relates to a semiconductor device and a method of production of the same, more particularly the present invention relates to a so-called dual gate construction complementary metal oxide (CMOS) semiconductor device which has both a p-type conductivity and n-type conductivity and prevents mutual diffusion of impurities doped into the gate electrodes and to a method of production of the same.
2. Description of the Related Art
At the present time, many CMOS large-scale integrated circuits (LSI) adopt a "polycide" gate electrode structure comprised of a high melting point metal silicide layer and a polycrystalline silicon layer so as to reduce the resistance of the gate electrodes. The above-mentioned polycrystalline silicon layer normally is the same in conductivity at the pMOS side and the nMOS side. As such a polycrystalline silicon layer, use is made for example of an n-type polycrystalline silicon layer doped with phosphorus etc. to a high concentration.
The difference in the work function between n-type polycrystalline silicon and the silicon substrate side however differs depending on whether the conductivity of the substrate side is the n-type or the p-type. Further, the difference in the absolute values of the threshold values (Vth) of the PMOS side and nMOS side is also large. Therefore, before forming the gate electrodes, boron or other p-type conductivity impurity ions are injected into the surface of the semiconductor substrate forming the channel region so as to preadjust it so that the absolute values of the threshold values of the nMOS and pMOS sides become substantially the same.
Accordingly, a MOS transistor fabricated by this method is a surface channel type at the nMOS side and is a buried channel type with a shallow pn junction and a channel somewhat to the inside of the substrate from the surface at the pMOS side.
The higher degrees of integration achieved in recent years, however, has led to shorter lengths of gate electrodes even in CMOS LSIs. Along with this, suppression of the short channel effect has become a major problem.
In such current day CMOS LSIs, it has long been pointed out that buried channel type pMOSs are particularly susceptible to the short channel effect. This has become a major problem along with the advances made in shortening gate lengths. To overcome this problem, it is desirable to make both the pMOS and nMOS sides the surface channel type. Therefore, dual-gate electrode constructions giving the same conductivity for the channels and gate electrodes have come into use.
In such a surface channel type dual-gate electrode construction, a p-type or an n-type impurity is selectively doped into the lower layer of polycrystalline silicon separately for the pMOS side and nMOS side. These different conductivity impurity regions are connected with each other through a tungsten silicide (WSi.sub.x) or other silicide electrode layer provided at the top for reducing the resistance.
In the above-mentioned surface channel type dual-gate electrode construction, however, the later heat treatment such as the annealing for activating the source and drain regions causes the doped impurities with the different conductivities to diffuse in the lateral direction toward the opposite conductivity gates primarily through the upper silicide electrode layer. If this mutual diffusion occurs, this changes the work functions of the gate electrodes and causes a shift in the threshold voltages (Vth) which had been adjusted so give substantially the same absolute values. The so-called depletion of the gates causes an increase in the value of the static capacitance and obstructs the high speed operation of the LSI.
Various proposals have been made to deal with this.
For example, IEEE 1994 Symposium on VLSI, Digest of Technical Papers, pp. 117-118, describes a method of changing the composition of the silicide electrode layer (WSi.sub.x layer) on the gate electrodes to make the silicon concentration higher.
Further, Fujii et al., Spring 1994 41st Seminar on Applied Physics, Preprints of Papers, No. 2, p. 675, "Effect of Suppression of Lateral Diffusion of As by PolySi/WSix/PolySi Construction", described a method of forming a further polycrystalline silicon layer on the WSi.sub.x layer to form a PolySi/WSix/PolySi construction.
These methods, however, merely improve the construction or characteristics to make it difficult for the impurities to diffuse in the WSi.sub.x layer, that is, the path of diffusion of the impurities. They cannot really be said to fundamentally overcome the disadvantage of the occurrence of mutual diffusion. Accordingly, if higher degrees of integration are achieved and annealing conditions become further severer, there is a chance that this disadvantage will arise again.
Further, in the former method of changing the composition of the WSi.sub.x layer, the sheet resistance rises in value along with the increase of the ratio of the silicon. This is not desirable for a semiconductor device.